This application claims the priority of Korean Patent Application No. 2003-59833, filed on Aug. 28, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device using a VSS or VDD bit line precharge approachapproach.
2. Description of the Related Art
In general, a half VDD precharge approach is used to precharge a bit line in a memory device. As the operating voltage of the memory device decreases and the operating speed of the memory device increases, a VSS or VDD precharge approach instead of a half VDD precharge approach is used to improve the sensing speed of a sense amplifier and enhance the operating stability and charge sharing speed of the sense amplifier under low voltage and low temperature conditions. Here, VDD denotes a power voltage and VSS denotes a ground voltage.
The VSS or VDD precharge approach employs a reference cell and a half reference charge generator to sense data “0” and “1” by providing a half reference voltage to a storage node of the reference cell. A conventional VSS or VDD precharge approach is disclosed in U.S. Pat. No. 6,570,799.
FIG. 1 is a circuit diagram of a semiconductor memory device using a conventional VSS precharge approach. Referring to FIG. 1, reference characters M0 and M1 designate normal memory cells, and reference characters RM0 and RM1 designate reference cells. Reference character EQ designates a precharge circuit or an equalization circuit, reference character NS designates an N-type sense amplifier, and reference character PS designates a P-type sense amplifier.
While a precharge command is executed, if a signal REQ becomes logic “High”, N-channel metal oxide semiconductor (MOS) transistors T0 and T1 are turned on such that one-half the level of VDD is applied to storage nodes N0 and N1 and both a bit line BL and a complementary bit line BLB are precharged to VSS due to a signal PEQ having a logic “High”.
While an active command is executed, when a word line WL1 connected to a gate of a selected transistor in the memory cell M1 that is connected to the bit line BL is enabled, a word line RWL1 connected to a gate of a selected transistor in the reference cell RM1 that is connected to the complementary bit line BLB is also enabled at the same time. If data of the memory cell M1 is “0”, the bit line BL maintains a VSS level, and if the data of the memory cell M1 is “1”, the level of the bit line BL increases to VSS+ΔV due to charge sharing. On the other hand, the level of the complementary bit line BLB increases to VSS+ΔV/2 without regard to the data of the memory cell M1. Here, ΔV denotes a predetermined voltage. Accordingly, whether the data of the memory cell M1 is “0” or “1”, a voltage difference between the bit line BL and the complementary bit line BLB is always ΔV/2.
The conventional VSS or VDD precharge approach has the following disadvantages. First, good uniformity between the normal cells and the reference cells cannot be ensured since the storage nodes of the reference cells should be controlled in the state where the reference cells are disposed in a normal cell area. Second, it is not easy to connect the control transistors T0 and T1 to the storage nodes N0 and N1. Third, if there is a defect in the reference cells, the chips cannot be used even though there are many resources for repairing the normal cells. Fourth, the half reference voltage generator should be used to provide half reference voltage to the storage nodes of the reference cells.